The present invention relates to a level shi ft circuit, and more particularly to a level shift circuit which is operated by an input signal and an inversion input signal.
FIG. 10 shows a structural example of a conventional level shift circuit. This level shifter circuit has a level shifter section 101 that is constituted by four MOS transistors, that is PMOS transistors P81 and P82, and NMOS transistors N81 and N82.
The PMOS transistor P81 and the NMOS transistor N81 are series-connected to each other between power supply voltages VHH and VLL through a terminal of an inversion output signal OUT B. In the same manner, the PMOS transistor P82 and the NMOS transistor N82 are also series-connected between power supply voltages VHH and VLL through a terminal of an output signal OUT. Moreover, the output signal OUT also serves as an input for the gate of the PMOS transistor P81, and the inversion output signal OUT B also serves as an input for the gate of the PMOS transistor P82.
An input signal IN is inputted to the gate of the NMOS transistor N81. An inversion input signal IN B, obtained by inverting the input signal IN in an inverter section 102, is inputted to the gate of the NMOS transistor N82. The inverter section 102 has a construction in which a PMOS transistor P83 and a NMOS transistor N83 are series-connected to each other between power supply voltages VHL and VLL.
In the level shift circuit having the above-mentioned construction, upon receipt of a low-level (voltage VL) signal as the input signal IN, the NMOS transistor N81 is turned off. Moreover, the input signal IN is also applied to the gates of the PMOS transistor P83 and the NMOS transistor N83 of the inverter section 102 so that the PMOS transistor P83 is turned on while the NMOS transistor N83 is turned off. In other words, the output from the inverter section 102 forms an output voltage VHL with only the PMOS transistor P83 being turned on.
Consequently, the inversion input signal IN B with High level (voltage VHL), obtained by inverting the input signal IN, is inputted to the NMOS transistor N82 to turn it on. For this reason, on the drain side of the NMOS transistor N82, the level of the output signal OUT is set to the VLL level. The PMOS transistor P81 having the output signal OUT connected to the gate thereof is turned on, since the gate level is lowered to the VLL level, with the result that on the drain side thereof, the level of the inversion output signal OUT B is set to the VHH level. The PMOS transistor P82, which has the inversion output signal OUT B with the VHH level as its gate input, is turned off.
As described above, in the level shift circuit, upon receipt of the input signal IN with the low level (voltage VL), the output signal OUT B is set to the VLL level and the inversion output signal OUT is set to the VHH level; thus, they are stabilized. In contrast, in the case when the input signal IN goes to the high level (voltage VH), the output signal OUT is set to the VHH level, and the inversion output signal OUT B is set to the VLL level; thus, they are stabilized.
In the arrangement of FIG. 10, the inverter section 102 is used in order to obtain the inversion input signal IN B to be inputted to the gate of the NMOS transistor N82; however, as illustrated in FIG. 11, even in the case when the inverter section 102 is removed, the same level shift operation may be carried out by inputting the signal IN B from outside.
However, in the above-mentioned conventional level shift circuit shown in FIG. 10, in addition to the power supply voltages (VHH, VLL) used for the circuits after having been subjected to the level shift, another power supply voltage (VHL) used for the inverter section 102 that generates the inversion input signal used before the level shift. These power supplies need to be inputted to the level shift circuit from outside, resulting in an increase in the number of terminals in the circuits.
Moreover, in the level shift circuit shown in FIG. 11, the inversion input signal IN B is generated by an external circuit, and inputted to the level shift circuit; however, in this case, since most of the signals that need to be inputted from outside require inversion signals thereof, this also results in an increase in the number of terminals.
One objective of the present invention is to provide a level shift circuit which can achieve a reduction in the number of input terminals as well as low power consumption, by using a simplified circuit construction, and also to provide an image display device using such a level shift circuit.
In order to achieve the above-mentioned objective, a level shift circuit in accordance with the present invention is provided with: a level shifter means, having an input signal and an inversion input signal formed by inverting the high/low level of the input signal inputted thereto, with a first voltage that is a high power-supply voltage and a second voltage that is a low power-supply voltage being connected thereto, which, based upon the high/low level of the input signal and inversion input signal, switches the first voltage and the second voltage to output the resulting voltage; an inversion input signal generation means, having the input signal, either of the first voltage and the second voltage, and a third voltage that gives an output level corresponding to the low level or the high level of the inversion input signal, inputted thereto, which, based upon the high/low level of the input signal, switches the output voltage level so as to generate an inversion input signal formed by inverting the input signal; and a voltage-dividing means which voltage-divides and extracts the third voltage between the first and second voltages.
In the case when the input signal and the inversion input signal formed by inverting the input signal are required as input signals to the level shifter, the third voltage that gives the output level corresponding to the low level or the high level of the inversion input signal needs to be prepared in addition to the first and second voltages that give the low level or the high level of the output signal.
In conventional devices, the third voltage has been supplied as a power supply voltage supplied from outside the level shift circuit; therefore, the corresponding terminals have been required. However, in the above-mentioned construction, the third voltage is generated by the voltage-dividing processes based upon the first and second voltages carried out by the voltage-dividing means. For this reason, it is possible to eliminate the terminal through which the third voltage is inputted, and consequently to reduce the number of terminals in the level shift circuit.
Moreover, in the level-shift circuit of the present invention which, in response to the input signal inputted from outside, generates an inversion input signal that is the corresponding inversion signal inside thereof, and based upon the high/low level of the input signal and the inversion input signal, shifts the level of the input signal so as to output the resulting signal, the voltage, which gives the output level of the low level or high level of the inversion input signal, is generated by a resistance division from the power supply voltage that gives the output level of the output signal that has been level-shifted.
In the case when the input signal and inversion input signal are used in the conventional level shift circuit, with respect to the inversion input signal, two cases in which it is inputted from outside in the same manner as the input signal and in which it is generated inside thereof have been proposed. In the case when the inversion input signal is inputted from outside, the corresponding input terminal is required in the level shift circuit. Moreover, even in the case when the inversion input signal is generated inside thereof, in addition to the power-supply voltage for providing the output level of the output signal that has been level-shifted, another voltage for providing the output level of the low level or high level of the inversion input signal is required; consequently, the corresponding terminal for supplying this voltage is required.
In contrast, in the construction of the level shift circuit of the present invention, the voltage, which gives the output level of the low level or high level of the inversion input signal, is generated by a resistance division from the power supply voltage that gives the output level of the output signal that has been level-shifted. That is, in the above-mentioned level shift circuit, only the terminal for inputting the power supply voltage for providing the output level of the output signal that has been level-shifted is required, resulting in a reduction in the number of the terminals.
Moreover, an image display device in accordance with the present invention, which is an active-matrix-type image display device having display pixels arranged in a matrix format, is characterized in that the data signal driving circuit and the scanning signal driving circuit have the above-mentioned level shift circuit.
In the above-mentioned image display device, it is possible to reduce the number of terminals in the data signal driving circuit and the scanning signal driving circuit.